View CY8C20142_4249470.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CY8C20142
CapSense ExpressTM - 4 Configurable IOs
Features
Overview
The CapSense ExpressTM controller allows the control of 4 IOs configurable as capacitive sensing buttons or as GPIOs for driving LEDs or interrupt signals based on various button conditions. The GPIOs are also configurable for waking up the device from sleep based on an interrupt input. The user has the ability to configure buttons, outputs, and parameters, through specific commands sent to the I2C port. The IOs have the flexibility in mapping to capacitive buttons and as standard GPIO functions such as interrupt output or input, LED drive and digital mapping of input to output using simple logical operations. This enables easy PCB trace routing and reduces the PCB size and stack up. CapSense Express products are designed for easy integration into complex products.
4 configurable IOs supporting CapSense buttons LED drive Interrupt outputs WAKE on interrupt input User defined Input or output 2.4V to 5.25V operating voltage Industrial temperature range: -40C to +85C I2C slave interface for configuration Selectable to 50 kHz,100 kHz and 400 kHz. Reduce BOM cost Internal oscillator - no external oscillators or crystal Free development tool - no external tuning components Low Operating Current Active current: continuous sensor scan: 1.5 mA Sleep current: no scan, continuous sleep: 2.6 uA Available in 8-pin SOIC package

Architecture
The logic block diagram shows the internal architecture of CY8C20142. The user can configure registers with parameters needed to adjust the operation and sensitivity of the CapSense system. CY8C20142 supports a standard I2C serial communication interface that allows the host to configure the device and to read sensor information in real time through easy register access.
The CapSense Express Core
The CapSense Express Core has a powerful configuration and control block. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers. System resources provide additional capability, such as a configurable I2C slave communication interface and various system resets. The Analog System is composed of the CapSense PSoC block which supports capacitive sensing of up to 4 inputs.
Cypress Semiconductor Corporation Document Number: 001-32159 Rev. *B
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised March 11, 2008
[+] Feedback
CY8C20142
Logic Block Diagram
External Vcc 2.4 - 5.25V
CapSense ExpressTM Core
4 Configurable IOs
2KB Flash 512B SRAM
Document Number: 001-32159 Rev. *B
Page 2 of 10
[+] Feedback
CY8C20142
Pinouts
Figure 1. Pin Diagram - 8 SOIC
VSS I2C SCL I2C SDA GP1[0]
VDD GP0[1] GP0[0] GP1[1]
Table 1. Pin Definitions - 8 SOIC Pin No 1 2 3 4 5 6 7 8 Name VSS I2C SCL Ground connection I2C clock I2C data Configurable as CapSense or GPIO Configurable as CapSense or GPIO Configurable as CapSense or GPIO Configurable as CapSense or GPIO Supply Voltage Description
I2C SDA GP1[0] GP1[1] GP0[0] GP0[1] VDD
Document Number: 001-32159 Rev. *B
Page 3 of 10
[+] Feedback
CY8C20142
The CapSense Analog System
The CapSense analog system contains the capacitive sensing hardware which supports CapSense Successive Approximation (CSA) algorithm. This hardware performs capacitive sensing and scanning without requiring external components. Capacitive sensing is configurable on each GPIO pin.
I2C Interface
The two modes of operation for the I2C interface are:

Device register configuration and status read or write for controller Command execution
Additional System Resources
System resources provide additional capability useful to complete systems. Additional resources are low voltage detection and power on reset.

The I2C address is programmable during configuration. It can be locked to prevent accidental change by setting a flag in a configuration register.
CapSense Express Software Tool
An easy to use software tool integrated with PSoC Express is available for configuring and tuning CapSense Express devices. Refer to the Application Note AN42137 for details of the software tool.
The I C slave provides 50, 100, or 400 kHz communication over two wires. Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels and the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor.
2
CapSense Express Register Map
CapSense Express supports user configurable registers through which the device functionality and parameters are configured. For details, refer to CY8C201xx Register Reference document.
An internal 1.8V reference provides a stable internal reference so that capacitive sensing functionality is not affected by minor VDD changes.
Electrical Specifications
Absolute Maximum Ratings
Parameter TSTG Description Storage temperature Min -55 Typ 25 Max +100 Unit C Notes Higher storage temperatures reduce data retention time. Recommended storage temperature is +25C 25C (0C to 50C). Extended duration storage temperatures above 65C degrade reliability.
TA VDD VIO VIOZ IMIO ESD LU
Ambient temperature with power applied Supply voltage on VDD relative to VSS DC input voltage DC voltage applied to tri-state Maximum current into any GPIO pin Electro static discharge voltage Latch up current
-40 -0.5 VSS - 0.5 VSS - 0.5 -25 2000 -
- - - - - - -
+85 +6.0 VDD + 0.5 VDD + 0.5 +50 - 200
C V V V mA V mA Human body model ESD
Operating Temperature
Parameter TA TJ Description Ambient temperature Junction temperature Min -40 -40 Typ - - Max +85 +100 Unit C C Notes
Document Number: 001-32159 Rev. *B
Page 4 of 10
[+] Feedback
CY8C20142
DC Electrical Characteristics
DC Chip Level Specifications
Parameter VDD IDD ISB ISB ISB Description Supply voltage Supply current Sleep mode current with POR and LVD active. Mid temperature range Sleep mode current with POR and LVD active. Sleep mode current with POR and LVD active. Min 2.40 - - - - Typ - 1.5 2.6 2.8 5.2 Max 5.25 2.5 4 5 6.4 Unit V mA A A A Conditions are VDD = 3.0V, TA = 25C VDD = 2.55V, 0C < TA < 40C VDD = 3.3V, -40C < TA < 85C VDD = 5.25V, -40C < TA < 85C Notes
5V and 3.3V DC General Purpose IO Specifications
This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges:4.75V to 5.25V and -40C 3.0V, maximum of 20 mA source current in all IOs. IOH = 1 mA, VDD > 3.0V, maximum of 20 mA source current in all IOs. IOH < 10 A, VDD> 3.0V, maximum of 10 mA source current in all IOs. IOH = 5 mA, VDD > 3.0V, maximum of 20 mA source current in all IOs. IOH < 10 A, VDD> 3.1V, maximum of 4 IOs all sourcing 5mA. IOH = 5 mA, VDD > 3.1V, maximum of 20 mA source current in all IOs. IOH < 10 A, VDD > 3.0V, maximum of 20 mA source current in all IOs. IOH < 200 A, VDD > 3.0V, maximum of 20 mA source current in all IOs. V IOL = 20 mA, VDD > 3V, maximum of 60 mA sink current on even port pins and 60 mA sink current on odd port pins. VDD = 3.6 to 5.25V. VDD = 3.6 to 5.25V. Gross tested to 1 A. Package and pin dependent. Temp = 25C. Package and pin dependent. Temp = 25C Page 5 of 10 Notes
VOH6
2.2
-
-
V
VOH7
2.1
2.4
2.5
V
VOH8
2
-
-
V
VOL
-
-
0.75
VIL VIH VH IIL CIN COUT
Input low voltage Input high voltage Input hysteresis voltage Input leakage Capacitive load on pins as input Capacitive load on pins as output
- 2.0 - - 0.5 0.5
- - 140 1 1.7 1.7
0.8 - - - 5 5
V V mV nA pF pF
Document Number: 001-32159 Rev. *B
[+] Feedback
CY8C20142
2.7 DC General Purpose IO Specifications
This tables lists guaranteed maximum and minimum specifications for the voltage and temperature ranges:2.4V to 3.0V and -40CVOLP1
Low output voltage port 1 pins
-
-
0.4
V
VIL VIH VIL VIH1 VIH2 VH IIL CIN COUT
Input low voltage Input high voltage Input low voltage Input high voltage Input high voltage Input hysteresis voltage Input leakage Capacitive load on pins as input Capacitive load on pins as output
- 1.6 - 1.4 1.6 - - 0.5 0.5
- - - - - 60 1 1.7 1.7
0.75 - 0.75 - - - - 5 5
V V V V V mV nA pF pF
DC POR & LVD Specifications
Parameter VPPOR0 VPPOR1 VLVD0 VLVD2 VLVD6 Description VDD Value for PPOR Trip VDD= 2.7V VDD= 3.3V, 5V VDD Value for LVD trip VDD= 2.7V VDD= 3.3V VDD= 5V Min - - 2.39 2.75 3.98 Typ 2.36 2.60 2.45 2.92 4.05 Max 2.40 2.65 2.51 2.99 4.12 Unit V V V V V Notes VDD must be greater than or equal to 2.5V during startup, reset from the XRES pin, or reset from Watchdog.
Document Number: 001-32159 Rev. *B
Page 6 of 10
[+] Feedback
CY8C20142
5.0V and 3.3V AC General Purpose IO Specifications Parameter TRise0 TRise1 TFall Description Rise time, strong mode, Cload = 50pF, Port 0 Rise time, strong mode, Cload = 50pF, Port 1 Fall time, strong mode, Cload = 50pF, all ports Min 15 10 10 Max 80 50 50 Unit ns ns ns Notes VDD = 3.0V to 3.6V and 4.75V to 5.25V, 10% - 90% VDD = 3.0V to 3.6V, 10% - 90% VDD = 3.0V to 3.6V and 4.75V to 5.25V, 10% - 90%
2.7V AC General Purpose IO Specifications Parameter TRise0 TRise1 TFall Description Rise time, strong mode, Cload = 50pF, Port 0 Rise time, strong mode, Cload = 50pF, Port 1 Fall time, strong mode, Cload = 50pF, all ports Min 15 10 10 Max 100 70 70 Unit ns ns ns Notes VDD = 2.4V to 3.0V, 10% - 90% VDD = 2.4V to 3.0V, 10% - 90% VDD = 2.4V to 3.0V, 10% - 90%
AC I2C Specifications
Parameter FSCLI2C Description SCL clock frequency Standard Mode Min 0 4.0 Max 100 Fast Mode Min 0 0.6 Max 400 Unit Kbps s Notes Fast mode not supported for VDD < 3.0V
THDSTAI2C Hold time (repeated) START condition. After this period, the first clock pulse is generated. TLOWI2C THIGHI2C TSUSTAI2C LOW period of the SCL clock HIGH period of the SCL clock Setup time for a repeated START condition
4.7 4.0 4.7 0 250 4.0 4.7 -
-
1.3 0.6 0.6 0 100 0.6 1.3 0
50
s s s s ns s s ns
THDDATI2C Data hold time TSUDATI2C Data setup time TSUSTOI2C Setup time for STOP condition TBUFI2C TSPI2C BUS free time between a STOP and START condition Pulse width of spikes suppressed by the input filter
Document Number: 001-32159 Rev. *B
Page 7 of 10
[+] Feedback
CY8C20142
Figure 2. Definition for Timing for Fast/Standard Mode on the I2C Bus
Document Number: 001-32159 Rev. *B
Page 8 of 10
[+] Feedback
CY8C20142
Ordering Information
Ordering Code CY8C20142-SX1I Package Diagram 51-85066 Package Type 8 SOIC Operating Temperature Industrial
Thermal Impedances by Package
Package 8 SOIC
Note 1. TJ = TA + Power x JA
Typical JA[1] 127.22 C/W
Solder Reflow Peak Temperature
Package 8 SOIC Minimum Peak Temperature[2] 240 C Maximum Peak Temperature 260 C
Note 2. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 5C with Sn-Pb or 245 5C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.
Package Diagram
Figure 3. 8 - Pin (150-Mil) SOIC(51-85066)
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 3. REFERENCE JEDEC MS-012
0.230[5.842] 0.244[6.197]
0.150[3.810] 0.157[3.987]
4. PACKAGE WEIGHT 0.07gms
PART # S08.15 STANDARD PKG. 5 8 SZ08.15 LEAD FREE PKG.
0.189[4.800] 0.196[4.978]
SEATING PLANE
0.010[0.254] 0.016[0.406]
X 45
0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0~8 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249]
0.0138[0.350] 0.0192[0.487]
51-85066-*C
Document Number: 001-32159 Rev. *B
Page 9 of 10
[+] Feedback
CY8C20142
Document History Page
Document Title: CY8C20142 CapSense ExpressTM - 4 Configurable IOs Document Number: 001-32159 REV. ** *A ECN. 1494145 1773608 Orig. of Change TUP/AESA TUP/AESA New Datasheet Removed table - 3V DC General Purpose IO Specifications Updated Logic Block Diagram Updated table - DC POR and LVD Specifications Updated table - DC Chip Level Specifications Updated table - 5V and 3.3V DC General Purpose IO Specifications Updated table - 2.7V DC General Purpose IO Specifications Updated table - AC GPIO Specifications and split it into two tables for 5V/3.3V and 2.7V Added section on CapSense ExpressTM Software tool Updated table-DC Chip Level Specifications Updated table-Pin Definitions 16 pin SOIC Updated table-5V and 3.3V DC General Purpose IO Specifications Updated table - 2.7V DC General Purpose IO Specifications Changed definition for Timing for Fast/Standard Mode on the I2C Bus diagram Description of Change
*B
2091026
DZU/MOHD /AESA
(c) Cypress Semiconductor Corporation, 2007-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-32159 Rev. *B
Revised March 11, 2008
Page 10 of 10
PSoC DesignerTM, Programmable System-on-ChipTM, and PSoC ExpressTM are trademarks and PSoC(R) is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective holders.
[+] Feedback

▲Up To Search▲

Price & Availability of CY8C20142

	To Download CY8C20142 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .